The present invention relates to a method of producing a semiconductor integrated circuit device and, more particularly, to an improvement of forming a interlayer insulating film covering a semiconductor body having a non-even surface.
In recent years, along with advancements in semiconductor integrated circuit devices, fine patterning of circuit elements and wiring layers has been required more and more to enhance the integration density of the device. A multi-level wiring structure has also become important to interconnect a great number of circuit elements to one another. In order to realize the multi-level wiring structure, at least one interlayer insulating film is required to isolate the lower-level and upper-level wiring layers from each layer.
However, when the semiconductor substrate has a large stop at the surface thereof due to circuit elements formed on the substrate, not in the substrate, undesired conductive films frequently remain on the interlayer insulating film. This drawback will be described in detail below with reference to FIG. 6 illustrating a conventional dynamic memory (DRAM) device.
As shown in FIG. 6A, a semiconductor device shown therein has a memory cell forming region 100 and a peripheral circuit forming region 101. These regions 100 and 101 as well as the respective circuit elements therein are separated by selectively forming a field oxide film 10 on a silicon substrate 9. A plurality of memory cell MOS transistors and associate storage capacitors are formed in the memory cell forming region 100. Each of the MOS transistor includes a pair of n-type source and drain regions 13-1 and 13-2 and a gate electrode 12 formed on a gate oxide film 11. The capacitor has a lower electrode (consisting of a polycrystalline silicon film 17, a sidewall 21 and a polycrystalline silicon film 23), an upper electrode 25 and a dielectric film 22 therebetween. This capacitor is of a stacked capacitor to present a relatively large capacitance value with the reduced occupation area. Thus, the storage capacitor is formed on the substrate so that the upper electrode thereof positioned at a level higher than the principal surface of the silicon substrate. A MOS transistor is also formed in the peripheral region. Next, an interlayer insulating film 30 such as a silicon oxide film is formed over the whole surface of the memory cell and the peripheral regions 100 and 101 by the chemical vapor deposition (CVD) method, followed by coating a photoresist film 31. Subsequently, the resist film 31 is patterned to have a plurality of contact holes and/or via-holes, and the insulating film 30 is then selectively removed by using the patterned photoresist film 31 as a mask.
Thereafter, an aluminum layer is deposited over the entire surface and then patterned to form a plurality of wiring layers 29-1 and 29-2, as shown in FIG. 6B.
Since the silicon oxide film 30 by the CVD method is formed with the substantially uniform thickness (for example, 0.8 .mu.m) over the memory cell region and the peripheral region, the surface shape of the underlying substrate reflects the surface shape of the film 30. For this reason, the oxide film 30 also has a large step at the surface thereof. On the other hand, the photoresist film 30 is not formed with a uniform thickness, but the portion thereof covering the step is made thick, as shown in FIG. 6A. For this reason, deviation in focus in the photolithography for patterning the photoresist film on the Aluminum layer occurs, so that undesired conductive layers 32 remain on the interlayer insulating film 30, as shown in FIG. 6B.
In order to make the surface of the insulating film flat, it is proposed to use a spin-on-glass (SOG) film, but it is difficult in practice to achieve sufficient flatness.